15th Euromicro Conference on
Digital System Design (DSD): Architectures; Methods & Tools
Izmir, Turkey, 5-8 September 2012

Call For Paper


The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed hardware/software system engineering, down to micro-architectures, digital circuits and VLSI techniques. It is a discussion forum for researchers and engineers from academia and industry working on state-of-the-art investigations, development and applications. It focuses on advanced circuit and system design and design automation concepts, paradigms, methods and tools, as well as on modern implementation technologies from full custom in nanometer technology nodes to FPGA and to multi-core infrastructures.
Compiler assisted ASIP, CMP, SMP, SMT, DSP-VLIW, GPU, platform based system design research results and application analysis and parallelization for embedded hardware and software design are welcome.
Design and Verification Languages and Standards, High Level Synthesis, Efficiency, Density, Signal Integrity, Testability, Timing Analysis and Timing Closure, Asynchronous Techniques, Reconfigurable Architectures, Power Consumption, Computational Power Speed and Performance, Productive Design Technology and Engineering Flows, Manufacturability, Cost, Reliability, Error Resilience, Complexity, or Process Variability issues, Modeling, Design Experiences are covered in DSD.

Main Topics

T1: (RC) Programmable/re-configurable/adaptable architectures
T2: (AP-HwSw) Application analysis and parallelization for embedded and high-performance design
T3: (SHES) System, hardware and embedded software design and automatic synthesis.
T4: (SoC & NoC) Systems-on-a-chip and networks-on-a-chip.
T5: (SMVT) System, hardware and embedded-software specification, modeling, verification and test.
T6: (APP) Applications of (embedded) digital systems.
T7: (ET) Important issues introduced by emerging technologies.

Special Sessions (SS web site)

SS1: (FDR) Flexible Digital Radio.
SS2: (MSDA) Multicore Systems: Design and Applications
SS3: (DTDS) Dependability and Testing of Digital Systems
SS4: (FTDSD) Fault Tolerance in Digital System Design
SS5: (SEO-WN) System-level Energy Optimization and Wireless Sensor Networks
SS6: (AHSA) Architectures and Hardware for Security Applications
SS7: (MoRPS) Monitoring and Reconfiguration of Parallel Systems
SS8: (DCPS) Design of Heterogeneous Cyber-Physical Systems
SS9 (EPDSD): European Projects in Digital System Design (invited papers only)

Submission Guidelines

Prospective authors are encouraged to submit their manuscripts for review electronically through the following web page (http://www.univ-valenciennes.fr/dsd2012/) or by sending the paper to the Session Chair via email (smail.niar@univ-valenciennes.fr) only if an unexpected web access problem is encountered) before the deadline for submission.
Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the required IEEE format: single-spaced, double column, A4/US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors' names should appear in the submitted manuscript, references included.

Important Dates

DSD Steering Committee

DSD 2012 Program Chair

DSD 2012 General Chair

Special Session 2012 Program Chairs:

DSD 2012 Program Committee

P. Athanas, Virginia Tech (US)
H. Basson, U. of Littoral (FR)
L. Benini, U. of Bologna (IT)
M. Berekovic, TU Braunschweig (DE)
N. Bergmann, U. of Queensland (AU)
C. Bouganis, Imperial College (UK)
P. Carballo, U. of Las Palmas GC (ES)
L. Carro, UFRGS (BR)
L. Chen, National Taiwan U. (TW)
C. Cornelius, U. of Rostock (DE)
G. Danese, U. Of Pavia (IT)
B. De Sutter, Ghent U. (BE)
J.L. Dekeyser, U. of Lille (FR)
R. Drechsler, U. of Bremen(DE)
N. Dutt, U. of Calif.(US)
TL. Fanucci, U. of Pisa (IT)
M. Figueroa, U. of Concepcion (CL)
J. Haid, Infineon Technologies (AT)
I. Hamzaoglu Sabanci U. (TK)
D. Houzet, Grenoble Inst. of Tech. (FR)
L. Jozwiak, Eindh. U. of Tech. (NL)
B. Juurlink, TU Berlin (DE)
K. Kent, U. of New Brunswick, (CA)
P. Kitsos, Hellenic Open U. (GR)
Z. Kotasek, Brno U. of Tech. (CZ)
H. Kubatova, CTU Prague (CZ)
K. Kuchcinski, Lund U. (SE)
S. Kumar, Jonkoping U. (SE)
A. Lastovetsky, U. College Dublin(IR)
F. Leporati, U. of Pavia (IT)
E.Levin, U. of Tel-Aviv (IS)
S. Lopez, IUMA/U. of Las Palmas (ES)
W. Luk, Imperial College (UK)
E. Martins, U. of Aveiro (PT)
J.S. Matos, U. of Porto (PT)
M.K.Michael, U. of Cyprus (CY)
H.E.Michail, Cyprus U. of Technology (CY)
T.Mitra, U. of Singapor (SG)
V. Muthukumar, U. Nevada (US)
N. Nedjah, U. of Rio de Janeiro (BR)
S. Niar, U. Valenciennes, (FR)
D. Noguet, Minatec CEA-LETI (FR)
A. Nunez, U. of Las Palmas G.C. (ES)
A. Orailoglu, U. of California (US)
O. Ozturk , Bilkent Univ Ankara (TR)
A. Pawlak, ITE & SUT (PL)
K. Popovici, Mathworks Inc. (US)
A. Postula, U. of Queensland (AU)
Y. Qu, Renesas Mobile (FI)
D. Quaglia, U. of Verona(IT)
J. Rabaey, U. of California (US)
J. Sahuquillo, Tech. U. of Valencia (ES)
T. Sasao, Kyushu Ins. of Tech. (JP)
C.Silvano, Polyt. Milano (IT)
A. Shrivastava, Arizona State U. (US)
N. Sklavos, Tech. Inst. Patras (GR)
L. Sousa, U. of Lisboa (PT)
W. Stechele, T. U. Munich (DE)
R. Ubar, Tallinn Tech. U. (EE)
M. Valero, Pol. U. of Catalunya (ES)
M. Velev, Aries Design Automa (US)
H.T. Vierhaus, BTU Cottbus (DE)
S. Vitabile, U. of Palermo (IT)
C. Wolinski, IRISA (FR)

DSD 2012 Web Administrator