Publications

• Article dans une revue

Fabrication and room-temperature single-charging behavior of self-aligned single-dot memory devices

Xing Tang, N. Reckinger, V. Bayot, Christophe Krzeminski, Emmanuel Dubois, A. Villaret, D.C. Bensahel

Self-aligned single-dot memory devices and arrays were fabricated based on arsenic-assisted etching and oxidation effects. The resulting device has a floating gate of about 5-10 nm, presenting single-electron memory operation at room temperature. In order to realize the final single-electron memory…

IEEE Transactions on Nanotechnology, 2006, 5 (6), pp.649-656. ⟨10.1109/TNANO.2006.883481⟩. ⟨hal-00138655⟩

• Article dans une revue

An optimal high contrast e-beam lithography process for the patterning of dense fin networks

F. Fruleux, J. Penaud, Emmanuel Dubois, M. Francois, M. Muller

There are many difficulties to overcome towards the integration of 10 nm CMOS technology. One such major challenge is to keep a tight control of the leakage current of devices while increasing the current drive at a reduced supply voltage. In this context, multi-gated structures, which are used to…

Materials Science and Engineering: C, 2006, 26 (5-7), pp.893-897. ⟨10.1016/j.msec.2005.09.017⟩. ⟨hal-00138653⟩

• Communication dans un congrès

Growth of molecular nanostructures on Si using SAMs of long-chain alkytrichlorosilanes

L. Patrone, S. Desbief, D. Goguenheim, D. Vuillaume

Trends in NanoTechnologies, TNT2006, 2006, Grenoble, France. ⟨hal-00127136⟩

• Article dans une revue

Electroformation of giant liposomes in microfluidic channels

K. Kuribayashi, G. Tresset, P. Coquet, H. Fujita, S. Takeuchi

Measurement Science and Technology, 2006, 17, pp.3121-3126. ⟨10.1088/0957-0233/17/12/S01⟩. ⟨hal-00244016⟩

• Thèse

Utilisation des technologies CMOS SOI 130 nm pour des applications en gamme de fréquences millimétriques, 130 nm SOI CMOS technology for microwaves applications

Christophe Pavageau

La technologie CMOS SOI (« Silicon On Insulator ») a déjà montré son intérêt pour les circuits numériques par rapport à la technologie CMOS sur substrat massif (« bulk »). Avec l'entrée des technologies CMOS dans l'ère des dimensions nanométriques, les transistors atteignent des…, Silicon On Insulator (SOI) CMOS technology has already shown good performances for digital applications compared to bulk CMOS technology. At nanometer-scale, SOI CMOS transistors exhibit very high cut-off frequencies, enabling the design of millimeter-wave integrated circuits and therefore the…

Micro et nanotechnologies/Microélectronique. Université des Sciences et Technologie de Lille - Lille I, 2005. Français. ⟨NNT : ⟩. ⟨tel-00011744v2⟩

• Communication dans un congrès

About the role played by the principles in the physics and mathematics by J.H. Poincaré

Raffaele Pisano

AIF Workshop Science & Teaching, 6th Dec., AIF Latina & GB Grassi Latina, Dec 2005, Latina, Italy. ⟨hal-04518908⟩

• Article dans une revue

Optimisation of the parameters of an extended defect model applied to non-amorphizing implants

E. Lampin, Fuccio Cristiano, Youness Lamrani, Damien Connétable

In this paper, we present the optimisation of the parameters of a physical model of the kinetics of extended defects and applied the model with the optimised parameters to non-amorphizing implants. The model describes the small clusters, the {113} defects and the dislocation loops. In the first…

Materials Science and Engineering: B, 2005, 124-125, pp.397-400. ⟨10.1016/j.mseb.2005.08.032⟩. ⟨hal-03599806⟩

• Article dans une revue

Planar excitation of Goubau transmission lines for THz BioMEMS

A. Treizebre, Tahsin Akalin, Bertrand Bocquet

We propose and demonstrate an original planar excitation of a single wire transmission line also known as Goubau-Line (G-Line). The excitation is based on an electromagnetic transition between a coplanar waveguide and the desired G-line in a planar configuration. We present some characteristics for…

IEEE Microwave and Wireless Components Letters, 2005, 15 (12), pp.886-888. ⟨10.1109/LMWC.2005.859976⟩. ⟨hal-00147496⟩

• Article dans une revue

130-nm partially depleted SOI MOSFET nonlinear model including the kink effect for linearity properties investigation

A. Siligaris, Gilles Dambrine, D. Schreurs, Francois Danneville

In this brief, a nonlinear empirical model is proposed for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs. It is based on an equivalent circuit approach in which the nonlinear elements are described by empirical equations. A new original method is proposed for modeling the kink effect…

IEEE Transactions on Electron Devices, 2005, 52 (12), pp.2809-2812. ⟨10.1109/TED.2005.859707⟩. ⟨hal-00125134⟩

• Article dans une revue

Impact of large angle tilt implantation on the threshold voltages of LDMOS transistors on SOI

H. Xu, E. Lampin, Emmanuel Dubois, S. Bardy, F. Murray

A purely vertical (0°) implantation and a large-angle tilt implantation (LATID) (usually 45°) are used to form the short channel of an LDMOS transistor. A modelling of both implantations is first carried on taking into account the geometrical effects of the LATID as well as the strong channelling…

Materials Science and Engineering: B, 2005, 124-125, pp.323-326. ⟨10.1016/j.mseb.2005.08.036⟩. ⟨hal-00138396⟩