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Lin-analyzer: A high-level performance analysis tool for FPGA-based accelerators

Guanwen Zhong, Alok Prakash, Yun-Kuan Liang, Tulika Mitra, Smail Niar

The increasing complexity of FPGA-based accelerators, coupled with time-to-market pressure, makes high-level synthesis (HLS) an attractive solution to improve designer productivity by abstracting the programming effort above registertransfer level (RTL). HLS offers various architectural design…

DAC '16: The 53rd Annual Design Automation Conference 2016, Jun 2016, Austin, Texas, United States. pp.1-6, ⟨10.1145/2897937.2898040⟩. ⟨hal-03383373⟩